/******************************************************************************
 ** File Name:      pinmap_pike2.h                                            *
 ** Author:         changzhengdong.rda                                        *
 ** DATE:           09/27/2017                                                *
 ** Copyright:      2004 Spreatrum, Incoporated. All Rights Reserved.         *
 ** Description:    This file defines the structure of pin map.               *
 ******************************************************************************

 ******************************************************************************
 **                        Edit History                                       *
 ** ------------------------------------------------------------------------- *
 ** DATE           NAME                DESCRIPTION                            *
 ** 03/08/2004     Richard.Yang        Create.                                *
 ** 09/27/2017     changzhengdong.rda  Version for Pike2.                     *
 ******************************************************************************/

#ifndef _PINMAP_H_
#define _PINMAP_H_

#include <linux/types.h>
#include "sprd_reg.h"
#include "adi.h"

typedef struct {
	uint32_t reg;
	uint32_t val;
} pinmap_t;
int pin_init(void);

#define CTL_PIN_BASE			(SPRD_PIN_PHYS)

/* registers definitions for controller CTL_PIN */
#define REG_PIN_CTRL0                   ( 0x0000 )
#define REG_PIN_CTRL1                   ( 0x0004 )
#define REG_PIN_CTRL2                   ( 0x0008 )
#define REG_PIN_CTRL3                   ( 0x000c )
#define REG_PIN_CTRL4                   ( 0x0010 )
#define REG_PIN_CTRL5                   ( 0x0014 )

/* registers definitions for controller CTL_PIN */
#define  REG_PIN_U0TXD               	( 0x0020 )
#define  REG_PIN_U0RXD               	( 0x0024 )
#define  REG_PIN_U0CTS               	( 0x0028 )
#define  REG_PIN_U0RTS               	( 0x002c )
#define  REG_PIN_MTCK_ARM            	( 0x0030 )
#define  REG_PIN_MTMS_ARM            	( 0x0034 )
#define  REG_PIN_PTEST               	( 0x0038 )
#define  REG_PIN_ANA_INT             	( 0x003c )
#define  REG_PIN_EXT_RST_B           	( 0x0040 )
#define  REG_PIN_CHIP_SLEEP          	( 0x0044 )
#define  REG_PIN_CLK_32K             	( 0x0048 )
#define  REG_PIN_AUD_SCLK            	( 0x004c )
#define  REG_PIN_AUD_ADD0            	( 0x0050 )
#define  REG_PIN_AUD_ADSYNC          	( 0x0054 )
#define  REG_PIN_AUD_DAD1            	( 0x0058 )
#define  REG_PIN_AUD_DAD0            	( 0x005c )
#define  REG_PIN_AUD_DASYNC          	( 0x0060 )
#define  REG_PIN_ADI_D               	( 0x0064 )
#define  REG_PIN_ADI_SYNC            	( 0x0068 )
#define  REG_PIN_ADI_SCLK            	( 0x006c )
#define  REG_PIN_SIMDA0              	( 0x0070 )
#define  REG_PIN_SIMCLK0             	( 0x0074 )
#define  REG_PIN_SIMRST0             	( 0x0078 )
#define  REG_PIN_SIMDA1              	( 0x007c )
#define  REG_PIN_SIMRST1             	( 0x0080 )
#define  REG_PIN_SIMCLK1             	( 0x0084 )
#define  REG_PIN_SIMCLK2             	( 0x0088 )
#define  REG_PIN_SIMDA2              	( 0x008c )
#define  REG_PIN_SIMRST2             	( 0x0090 )
#define  REG_PIN_NF_DATA_2           	( 0x0094 )
#define  REG_PIN_NF_DATA_1           	( 0x0098 )
#define  REG_PIN_NF_DATA_0           	( 0x009c )
#define  REG_PIN_NF_WEN              	( 0x00a0 )
#define  REG_PIN_NF_CEN0             	( 0x00a4 )
#define  REG_PIN_EMMC_DUMMY          	( 0x00a8 )
#define  REG_PIN_EMMC_D0             	( 0x00ac )
#define  REG_PIN_EMMC_D1             	( 0x00b0 )
#define  REG_PIN_EMMC_D2                ( 0x00b4 )
#define  REG_PIN_EMMC_D3            	( 0x00b8 )
#define  REG_PIN_EMMC_D4            	( 0x00bc )
#define  REG_PIN_EMMC_D5            	( 0x00c0 )
#define  REG_PIN_EMMC_D6            	( 0x00c4 )
#define  REG_PIN_EMMC_D7            	( 0x00c8 )
#define  REG_PIN_EMMC_CLK           	( 0x00cc )
#define  REG_PIN_EMMC_DS            	( 0x00d0 )
#define  REG_PIN_EMMC_CMD           	( 0x00d4 )
#define  REG_PIN_EMMC_RST           	( 0x00d8 )
#define  REG_PIN_LCM_RSTN           	( 0x00dc )
#define  REG_PIN_DSI_TE             	( 0x00e0 )
#define  REG_PIN_SCL0               	( 0x00e4 )
#define  REG_PIN_SDA0               	( 0x00e8 )
#define  REG_PIN_CMMCLK0            	( 0x00ec )
#define  REG_PIN_CMRST0             	( 0x00f0 )
#define  REG_PIN_CMPD0              	( 0x00f4 )
#define  REG_PIN_CMPD1              	( 0x00f8 )
#define  REG_PIN_SD0_CLK0           	( 0x00fc )
#define  REG_PIN_SD0_CMD            	( 0x0100 )
#define  REG_PIN_SD0_D0             	( 0x0104 )
#define  REG_PIN_SD0_D1             	( 0x0108 )
#define  REG_PIN_SD0_D2             	( 0x010c )
#define  REG_PIN_SD0_D3             	( 0x0110 )
#define  REG_PIN_SD0_DUMMY          	( 0x0114 )
#define  REG_PIN_IIS0CLK            	( 0x0118 )
#define  REG_PIN_IIS0LRCK           	( 0x011c )
#define  REG_PIN_IIS0DI             	( 0x0120 )
#define  REG_PIN_IIS0DO             	( 0x0124 )
#define  REG_PIN_U1RXD              	( 0x0128 )
#define  REG_PIN_U1TXD              	( 0x012c )
#define  REG_PIN_KEYIN0             	( 0x0130 )
#define  REG_PIN_KEYIN1             	( 0x0134 )
#define  REG_PIN_KEYIN2             	( 0x0138 )
#define  REG_PIN_KEYOUT0            	( 0x013c )
#define  REG_PIN_KEYOUT1            	( 0x0140 )
#define  REG_PIN_KEYOUT2            	( 0x0144 )
#define  REG_PIN_LNA_EN             	( 0x0148 )
#define  REG_PIN_SPI_HS_DO          	( 0x014c )
#define  REG_PIN_SPI_HS_DI          	( 0x0150 )
#define  REG_PIN_SPI_HS_CLK         	( 0x0154 )
#define  REG_PIN_SPI_HS_CSN         	( 0x0158 )
#define  REG_PIN_EXTINT1            	( 0x015c )
#define  REG_PIN_EXTINT0            	( 0x0160 )
#define  REG_PIN_SCL2               	( 0x0164 )
#define  REG_PIN_SDA2               	( 0x0168 )
#define  REG_PIN_SCL1               	( 0x016c )
#define  REG_PIN_SDA1               	( 0x0170 )
#define  REG_PIN_RFCTL11            	( 0x0174 )
#define  REG_PIN_RFCTL10            	( 0x0178 )
#define  REG_PIN_RFCTL9             	( 0x017c )
#define  REG_PIN_RFCTL8             	( 0x0180 )
#define  REG_PIN_RFCTL7             	( 0x0184 )
#define  REG_PIN_RFCTL6             	( 0x0188 )
#define  REG_PIN_RFCTL5             	( 0x018c )
#define  REG_PIN_RFCTL4             	( 0x0190 )
#define  REG_PIN_RFCTL3             	( 0x0194 )
#define  REG_PIN_RFCTL2             	( 0x0198 )
#define  REG_PIN_RFCTL1             	( 0x019c )
#define  REG_PIN_RFCTL0             	( 0x01a0 )

/* registers definitions for controller CTL_PIN MISC_OFFSET */
#define  REG_MISC_PIN_U0TXD               	( 0x0420 )
#define  REG_MISC_PIN_U0RXD               	( 0x0424 )
#define  REG_MISC_PIN_U0CTS               	( 0x0428 )
#define  REG_MISC_PIN_U0RTS               	( 0x042c )
#define  REG_MISC_PIN_MTCK_ARM            	( 0x0430 )
#define  REG_MISC_PIN_MTMS_ARM            	( 0x0434 )
#define  REG_MISC_PIN_PTEST               	( 0x0438 )
#define  REG_MISC_PIN_ANA_INT             	( 0x043c )
#define  REG_MISC_PIN_EXT_RST_B           	( 0x0440 )
#define  REG_MISC_PIN_CHIP_SLEEP          	( 0x0444 )
#define  REG_MISC_PIN_CLK_32K             	( 0x0448 )
#define  REG_MISC_PIN_AUD_SCLK            	( 0x044c )
#define  REG_MISC_PIN_AUD_ADD0            	( 0x0450 )
#define  REG_MISC_PIN_AUD_ADSYNC          	( 0x0454 )
#define  REG_MISC_PIN_AUD_DAD1            	( 0x0458 )
#define  REG_MISC_PIN_AUD_DAD0            	( 0x045c )
#define  REG_MISC_PIN_AUD_DASYNC          	( 0x0460 )
#define  REG_MISC_PIN_ADI_D               	( 0x0464 )
#define  REG_MISC_PIN_ADI_SYNC            	( 0x0468 )
#define  REG_MISC_PIN_ADI_SCLK            	( 0x046c )
#define  REG_MISC_PIN_SIMDA0              	( 0x0470 )
#define  REG_MISC_PIN_SIMCLK0             	( 0x0474 )
#define  REG_MISC_PIN_SIMRST0             	( 0x0478 )
#define  REG_MISC_PIN_SIMDA1              	( 0x047c )
#define  REG_MISC_PIN_SIMRST1             	( 0x0480 )
#define  REG_MISC_PIN_SIMCLK1             	( 0x0484 )
#define  REG_MISC_PIN_SIMCLK2             	( 0x0488 )
#define  REG_MISC_PIN_SIMDA2              	( 0x048c )
#define  REG_MISC_PIN_SIMRST2             	( 0x0490 )
#define  REG_MISC_PIN_NF_DATA_2           	( 0x0494 )
#define  REG_MISC_PIN_NF_DATA_1           	( 0x0498 )
#define  REG_MISC_PIN_NF_DATA_0           	( 0x049c )
#define  REG_MISC_PIN_NF_WEN              	( 0x04a0 )
#define  REG_MISC_PIN_NF_CEN0             	( 0x04a4 )
#define  REG_MISC_PIN_EMMC_DUMMY          	( 0x04a8 )
#define  REG_MISC_PIN_EMMC_D0             	( 0x04ac )
#define  REG_MISC_PIN_EMMC_D1             	( 0x04b0 )
#define  REG_MISC_PIN_EMMC_D2               	( 0x04b4 )
#define  REG_MISC_PIN_EMMC_D3            	( 0x04b8 )
#define  REG_MISC_PIN_EMMC_D4            	( 0x04bc )
#define  REG_MISC_PIN_EMMC_D5            	( 0x04c0 )
#define  REG_MISC_PIN_EMMC_D6            	( 0x04c4 )
#define  REG_MISC_PIN_EMMC_D7            	( 0x04c8 )
#define  REG_MISC_PIN_EMMC_CLK           	( 0x04cc )
#define  REG_MISC_PIN_EMMC_DS            	( 0x04d0 )
#define  REG_MISC_PIN_EMMC_CMD           	( 0x04d4 )
#define  REG_MISC_PIN_EMMC_RST           	( 0x04d8 )
#define  REG_MISC_PIN_LCM_RSTN           	( 0x04dc )
#define  REG_MISC_PIN_DSI_TE             	( 0x04e0 )
#define  REG_MISC_PIN_SCL0               	( 0x04e4 )
#define  REG_MISC_PIN_SDA0               	( 0x04e8 )
#define  REG_MISC_PIN_CMMCLK0            	( 0x04ec )
#define  REG_MISC_PIN_CMRST0             	( 0x04f0 )
#define  REG_MISC_PIN_CMPD0              	( 0x04f4 )
#define  REG_MISC_PIN_CMPD1              	( 0x04f8 )
#define  REG_MISC_PIN_SD0_CLK0           	( 0x04fc )
#define  REG_MISC_PIN_SD0_CMD            	( 0x0500 )
#define  REG_MISC_PIN_SD0_D0             	( 0x0504 )
#define  REG_MISC_PIN_SD0_D1             	( 0x0508 )
#define  REG_MISC_PIN_SD0_D2             	( 0x050c )
#define  REG_MISC_PIN_SD0_D3             	( 0x0510 )
#define  REG_MISC_PIN_SD0_DUMMY          	( 0x0514 )
#define  REG_MISC_PIN_IIS0CLK            	( 0x0518 )
#define  REG_MISC_PIN_IIS0LRCK           	( 0x051c )
#define  REG_MISC_PIN_IIS0DI             	( 0x0520 )
#define  REG_MISC_PIN_IIS0DO             	( 0x0524 )
#define  REG_MISC_PIN_U1RXD              	( 0x0528 )
#define  REG_MISC_PIN_U1TXD              	( 0x052c )
#define  REG_MISC_PIN_KEYIN0             	( 0x0530 )
#define  REG_MISC_PIN_KEYIN1             	( 0x0534 )
#define  REG_MISC_PIN_KEYIN2             	( 0x0538 )
#define  REG_MISC_PIN_KEYOUT0            	( 0x053c )
#define  REG_MISC_PIN_KEYOUT1            	( 0x0540 )
#define  REG_MISC_PIN_KEYOUT2            	( 0x0544 )
#define  REG_MISC_PIN_LNA_EN             	( 0x0548 )
#define  REG_MISC_PIN_SPI_HS_DO          	( 0x054c )
#define  REG_MISC_PIN_SPI_HS_DI          	( 0x0550 )
#define  REG_MISC_PIN_SPI_HS_CLK         	( 0x0554 )
#define  REG_MISC_PIN_SPI_HS_CSN         	( 0x0558 )
#define  REG_MISC_PIN_EXTINT1            	( 0x055c )
#define  REG_MISC_PIN_EXTINT0            	( 0x0560 )
#define  REG_MISC_PIN_SCL2               	( 0x0564 )
#define  REG_MISC_PIN_SDA2               	( 0x0568 )
#define  REG_MISC_PIN_SCL1               	( 0x056c )
#define  REG_MISC_PIN_SDA1               	( 0x0570 )
#define  REG_MISC_PIN_RFCTL11            	( 0x0574 )
#define  REG_MISC_PIN_RFCTL10            	( 0x0578 )
#define  REG_MISC_PIN_RFCTL9             	( 0x057c )
#define  REG_MISC_PIN_RFCTL8             	( 0x0580 )
#define  REG_MISC_PIN_RFCTL7             	( 0x0584 )
#define  REG_MISC_PIN_RFCTL6             	( 0x0588 )
#define  REG_MISC_PIN_RFCTL5             	( 0x058c )
#define  REG_MISC_PIN_RFCTL4             	( 0x0590 )
#define  REG_MISC_PIN_RFCTL3             	( 0x0594 )
#define  REG_MISC_PIN_RFCTL2             	( 0x0598 )
#define  REG_MISC_PIN_RFCTL1             	( 0x059c )
#define  REG_MISC_PIN_RFCTL0             	( 0x05a0 )

/* bits definitions for register REG_PIN_XXX */
#define BITS_PIN_DS(_x_)                ( ((_x_) << 19) & (BIT_19|BIT_20|BIT_21|BIT_22) )
#define BIT_PIN_SLP_WTLCP               ( BIT_15 )
#define BIT_PIN_SLP_PUBCP               ( BIT_14 )
#define BIT_PIN_SLP_AP                  ( BIT_13 )
#define BIT_PIN_SLP_NONE		( (~(0x7 << 13)) & (BIT_13|BIT_14|BIT_15) )
#define BITS_PIN_SLP(_x_)               ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15) )
#define BIT_PIN_WPUS                    ( BIT_12 )
#define BIT_PIN_WPU                     ( BIT_7 )
#define BIT_PIN_WPD                     ( BIT_6 )
#define BITS_PIN_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
#define BIT_PIN_SLP_WPU                 ( BIT_3 )
#define BIT_PIN_SLP_WPD                 ( BIT_2 )
#define BIT_PIN_SLP_IE                  ( BIT_1 )
#define BIT_PIN_SLP_OE                  ( BIT_0 )

/* vars definitions for controller CTL_PIN */
#define BIT_PIN_NUL                     ( 0 )
#define BIT_PIN_SLP_NUL                 ( 0 )
#define BIT_PIN_SLP_Z                   ( 0 )
#define BIT_PIN_NULL                    ( 0 )

#endif //_PINMAP_H_

